Data-dependent jitter pre-emphasis for high-speed serial link transmitters

ABSTRACT

In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

FIELD OF THE INVENTION

The present invention relates generally to data equalization techniquesfor high speed serial links.

BACKGROUND OF THE INVENTION

High bandwidth chip-to-chip interconnection is a crucial part of manysystems today. High speed inputs/outputs (I/Os) are extensively used inserver processors, memory-central processing unit (CPU) interfaces,multiprocessor systems, and gaming applications. With increasing speedof on-chip data processing, there is an increasing demand for higherdata rates. These high speed I/Os must also be capable of supporting lowcost package and board technologies which introduce large signaldegradation through bandwidth loss, reflection, and crosstalk.

Equalization of high-speed serial links has evolved to compensateinter-symbol interference (ISI) caused by frequency-dependentattenuation found in interconnects. Pre-emphasis-based equalization inthe transmitter and decision feedback equalization in the receiverfigure prominently in overcoming signal degradation and improving BitError Rate (BER). Currently, one challenge of equalization is minimizingpower consumption while still improving signal integrity in the presenceof attenuation and reflections.

Transmitters are a significant portion of the serial link power budget.The transmitter is required to drive enough power over lossyinterconnects to meet minimum receiver sensitivity requirements. The useof amplitude pre-emphasis techniques, such as feed forward equalization,increases the power consumption and chip area and places additionaldemands on the dynamic range of the transmitter. Also, in a transmissionsystem with high cross-talk between the channels, especially the nearend cross talk where a transmitter is leaking into a neighboringreceiver, amplitude pre-emphasis will enhance the high frequencycross-talk of the victim receiver which implies that its signal to noiseratio will be degraded.

In view of the foregoing, a growing need has been recognized inconnection with improving upon the shortcomings and disadvantagespresented by conventional arrangements.

SUMMARY OF THE INVENTION

In accordance with at least one presently preferred embodiment of theinvention, there is broadly contemplated an expansion of the notion ofpre-emphasis beyond conventional amplitude compensation of ISI, wherebyphase pre-emphasis for compensating data-dependent jitter (DDJ) isintroduced. DDJ can be addressed by exploiting the relationship betweenthe data sequence and the timing deviation. Phase pre-emphasis improvesthe signal integrity with little additional power consumption in thetransmitter and with no cross-talk penalty.

In summary, one aspect of the invention provides an apparatus forproviding data dependent jitter in data transmission, the apparatuscomprising: an input arrangement for accepting data input; anarrangement for detecting and decoding transitions in the data input;the arrangement for detecting and decoding being adapted to ascertaindata transition history in the data input; and an arrangement forapplying at least one delay to at least a portion of the data input,based on the ascertained data transition history.

Another aspect of the invention provides a method of providing datadependent jitter in data transmission, the method comprising the stepsof: accepting data input; detecting and decoding transitions in the datainput; the step of detecting and decoding comprising ascertaining datatransition history in the data input; and applying at least one delay toat least a portion of the data input, based on the ascertained datatransition history.

For a better understanding of the present invention, together with otherand further features and advantages thereof, reference is made to thefollowing description, taken in conjunction with the accompanyingdrawings, and the scope of the invention will be pointed out in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a schematic illustration of channel effect on data-dependentjitter.

FIG. 3 is a block diagram of a second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Generally speaking, in a link where losses due to signal attenuation aredominating other channel impairments such as reflection due todiscontinuities, the amount of DDJ of a random bit sequence at the endof a link, which corresponds to timing deviation from ideal transitiontime, depends on the previous bit sequences only. Thus, the amount ofDDJ at a given transition time corresponding to a given channel can bepredicted by simply keeping track of the previous transitions. Also, itcan be shown that the most recent transitions in previous data bitscontribute to DDJ with larger amount. Thus, most of the DDJ can bepredicted and compensated for by only detecting some of the most recenttransitions. For typical links, one needs to detect down to the threeprevious data transitions to predict most of the DDJ occurring at a thecurrent data transition.

Phase pre-emphasis manipulates the data transitions to neutralize DDJ atthe end of the transmission channel. The delay of the data transition tobe transmitted is dynamically changed depending on the previous bitsequence detected. In general, the highest frequency components of thedata sequence are delayed before being transmitted in such a way thatthe arrival time of the different frequency components of the datasequence closely coincide at the end of the link. This delay (or phase)pre-distortion will thus increase both the timing and voltage margins ofthe signal at the end of the link.

In accordance with one preferred embodiment of the present invention, afull-rate clock transmitter architecture approach shows how a serialtype phase pre-distortion is implemented. In accordance with a secondpreferred embodiment of the present invention, a quarter-clocktransmitter architecture shows how a parallel type phase pre-distortionis implemented.

FIG. 1 illustrates the aforementioned first embodiment, corresponding tothe front-end of a transmitter which performs phase pre-distortion onthe serial data that is transmitted over the transmission mediumpossibly using a line driver. As shown, there are preferably providedsingle data bit time delay elements 102, 103 and 104, XOR gates 105, 106and 107, a transition decoder 108 connected to outputs of XOR gates105/106/107, programmable tap weights 109 and a programmable delay line110.

Preferably, a serial data stream 101 is successively delayed by thesingle data bit delay elements 102, 103 and 104. Though only three delayelements are shown, the actual number of these delay elements can be ashigh as needed depending how many previous transitions need to bedetected in order to compute the pre-distortion delay to be applied tothe current bit. XOR gate 105 compares signal 101 to the output of 102to detect if a transition is occurring on the current bit to betransmitted. If a transition is present the output of XOR gate 105 willbe high. XOR gates 106, 107 function similarly to gate 105 but,respectively, compare signal outputs from delay elements 102/103 andfrom 103/104. As with gate 105, if a transition is detected then theoutput of gate 106 or 107 will be high, as appropriate. Then, dependingon the data transition history that is determined by the transitiondecoder 108, a pre-distortion delay is added or subtracted to thecurrent data transition time using the programmable delay line 110.

The amount of pre-distortion delay is programmed through theprogrammable tap weights 109 and depends on the transmission medium thatneeds to be equalized. Decoder 108 can be embodied and implemented inessentially any suitable manner. For instance, decoder 108 can employsimple Boolean logic to carry out its function as described above. Atthe same time, the amount of delay to be applied by delay line 110, oncethe data transition history is known, can depend on the channel at hand.As such, the delay could be pre-set or continuously optimized (if thetransmitter can receive information about the channel from the receivingend of the link).

For a typical transmission medium such as coaxial cable where the lossesare dominated by frequency dependent attenuation, the high frequencycomponents of a random data sequence arrive first at the end of thetransmission medium, while the slowest ones arrives later, asillustrated in the left-hand portion of FIG. 2. Thus, in theillustrative and non-restrictive example shown, the higher-frequencycomponent 250 arrives prior to component 252; the combined graph ofthese is indicated at 254. The aftereffect, if employed in accordancewith the arrangement of FIG. 1, is shown in the right-hand portion ofFIG. 2 upon exit from channel 256. Generally, the longest pre-distortiondelay is added to the transmitted bit when the transition decoder 108detects a transition on the previous bit, while the applied delay willbe comparably shorter to the extent that the previous transitiondetected by the transition decoder 108 occurs with “earlier” bits. Asshown, with “input” components 250 and 252 now transformed into “output”components 258 and 260, respectively, the former (258) has acomparatively greater delay applied, the result of which can beappreciated in the combined graph at 262 as well as the combined diagramat 264. The marked “DDJ” distance corresponds to this difference indelay. The “eye opening” is the region where data transitions are notpresent (when considering only DDJ and not jitter due to random noise);as such, data will be detected with no errors if sampled in this region.

FIG. 3 illustrates a second preferred embodiment of the presentinvention, corresponding to a quarter-rate transmitter which performsphase pre-distortion on the serial data that is transmitted over atransmission medium (e.g., via a line driver), while using thequarter-rate data to detect the transition history. Included are datalatches 301, 302, 303 and 304, a transition detector and decoder 305,programmable tap weights 306, programmable delay elements 307 and aquarter-rate 4:1 data multiplexer 308. Corresponding transmission graphsare illustrated to the right of the drawing. It should be clearlyunderstood that while an illustrative and non-restrictive example of aquarter-rate implementation is shown in FIG. 3, the present invention,in accordance with at least one presently preferred embodiment, ofcourse broadly embraces the implementation of essentially any workablearrangement involving parallel partial-rate data streams. Thus, forinstance, the use of two half-rate data streams, as opposed to fourquarter-rate streams, is conceivable in employing features discussedherein in connection with FIG. 3.

As shown, four parallel quarter-rate data streams D0, D1, D2 and D3 arereceived using sampling latches 301, 302, 303 and 304, respectively.These latches are not mandatory but are usually used to align theincoming parallel data to the local clock. As opposed to the firstembodiment where the transition decoder was operating on serializeddata, here the transition decoder 305 operates on the quarter-rate datastream to determine the data sequence to be transmitted through thechannel. (It should be understood that this quarter rate example couldbe extended to even wider parallel data at the input that would be thentime multiplexed before being transmitted.) Decoder 305 therebygenerates a code that is then passed to the programmable delay elements307 through the programmable tap weights 306 that will set the amount ofphase pre-distortion on the data depending on the transmission mediumused. To that end, the programmable delay elements 306 will pre-distortthe phase of the four quarter-rate clocks C4_0, C4_90, C4_180 and C4_270that are used to time multiplex the parallel quarter-rate data into ahigh speed serial data that is then transmitted through the transmissionmedium.

In recapitulation, there are broadly contemplated herein newequalization techniques involving phase pre-distortion as an alternativeto conventional amplitude pre-emphasis. These techniques are inparticular suitable for low power and low area serial link applications,especially when dealing with a lossy transmission medium that introducesexcessive pattern dependent jitter. Phase pre-distortion is less powerhungry than amplitude pre-emphasis and requires a smaller chip area.Also, phase pre-distortion does not degrade the signal to noise ratiodue to the enhancement of channel cross talk at high frequency that iscaused by amplitude pre-emphasis.

If not otherwise stated herein, it is to be assumed that all patents,patent applications, patent publications and other publications(including web-based publications) mentioned and cited herein are herebyfully incorporated by reference herein as if set forth in their entirelyherein.

Although illustrative embodiments of the present invention have beendescribed herein with reference to the accompanying drawings, it is tobe understood that the invention is not limited to those preciseembodiments, and that various other changes and modifications may beaffected therein by one skilled in the art without departing from thescope or spirit of the invention.

1. An apparatus for providing data dependent jitter in datatransmission, said apparatus comprising: an input arrangement foraccepting data input; an arrangement for detecting and decodingtransitions in the data input; said arrangement for detecting anddecoding being adapted to ascertain data transition history in the datainput; and an arrangement for applying at least one delay to at least aportion of the data input, based on the ascertained data transitionhistory.
 2. The apparatus according to claim 1, wherein the input datacomprises a serial data stream.
 3. The apparatus according to claim 2,wherein said input arrangement comprises a plurality of single data bitdelay elements for successively delaying the serial data stream of theinput data.
 4. The apparatus according to claim 3, wherein saiddetecting and decoding arrangement comprises a plurality of XOR gatesfor comparing portions of the serial data stream at different samplingpositions among said plurality of single data bit delay elements.
 5. Theapparatus according to claim 2, wherein said arrangement for applying atleast one delay is adapted to add or subtract a pre-distortion delay tothe serial data stream of the input data.
 6. The apparatus according toclaim 1, wherein the data input comprises a plurality of parallelpartial-rate data streams.
 7. The apparatus according to claim 6,wherein said input arrangement comprises a plurality of receivingelements for aligning the partial-rate data streams to a local clock. 8.The apparatus according to claim 6, wherein: said detecting and decodingarrangement is adapted to influence the partial-rate data streams todetermine a data sequence to be subsequently transmitted in an outputserial data stream; and said detecting and decoding arrangement isadapted to generate a code informing an amount of pre-phase distortionto be applied to the input data.
 9. The apparatus according to claim 6,wherein said arrangement for applying at least one delay is adapted topre-distort the phase of a clock used in transitioning the partial-ratedata streams into an output serial data stream.
 10. The apparatusaccording to claim 6, wherein the data input comprises a plurality ofparallel quarter-rate data streams.
 11. A method of providing datadependent jitter in data transmission, said method comprising the stepsof: accepting data input; detecting and decoding transitions in the datainput; said step of detecting and decoding comprising ascertaining datatransition history in the data input; and applying at least one delay toat least a portion of the data input, based on the ascertained datatransition history.
 12. The method according to claim 11, wherein thedata input comprises a serial data stream.
 13. The method according toclaim 12, wherein said accepting step comprises accepting a plurality ofsingle data bit delay elements for successively delaying the serial datastream of the input data.
 14. The method according to claim 13, whereinsaid detecting and decoding step comprises comparing portions of theserial data stream at different sampling positions among the pluralityof single data bit delay elements.
 15. The method according to claim 12,wherein said step of applying at least one delay comprises adding orsubtracting a pre-distortion delay to the serial data stream of theinput data.
 16. The method according to claim 11, wherein the data inputcomprises a plurality of parallel partial-rate data streams.
 17. Themethod according to claim 16, wherein said input step comprises aligningthe partial-rate data streams to a local clock.
 18. The method accordingto claim 16, wherein: said detecting and decoding step comprisesinfluencing the partial-rate data streams to determine a data sequenceto be subsequently transmitted in an output serial data stream; and saiddetecting and decoding step comprises generating a code informing anamount of pre-phase distortion to be applied to the input data.
 19. Themethod according to claim 16, wherein said step of applying at least onedelay comprises pre-distorting the phase of a clock used intransitioning the partial-rate data streams into an output serial datastream.
 20. The method according to claim 16, wherein the data inputcomprises a plurality of parallel quarter-rate data streams.